GEB Enterprise
Test BSCAN (JTAG)
Reduce timer to market using JTAG Test!
Boundary Scan Test Objectives
Overview of JTAG Test
The Boundary Scan Test overcomes the limit of accessibility typical of packages that BSCAN TEST BGA PACKAGEhave higher pin-counts and smaller pitches, such as BGA or QFP.
As example, the BGA is largely used for FPGA by millions of gates, for SOC (System On Chip) components, for SDRAM, DDRAM, Flash memories and I / O components as well. The μBGA package replaced the PQFP, PSOP and TQFP packages, even with lower pin-counts (<100).
The Boundary Scan Test (BSCAN) is not limited to the testing of the interconnections between components fitted with BSCAN interface: It also allows the testing of groups of digital components without BSCAN interface (also called CLUSTER), connected to the card connectors and/or BSCAN components.
The BSCAN pins of the components and connectors are used as a “virtual bed of nails” to stimulate and analyze the CLUSTER responses.
This allows functional testing of both simple components such as Gates, Registers, Counters, and complex components such as SRAM, DRAM, FIFO, EEPROM, FLASH, UART, etc …
The manufacturing testing is not the only application for the BSCAN standard; it is often adopted by the major suppliers of FPGA using the In-System Programming (ISP) and In-System Configuration (ISC ) methodologies. The Flash emulation and programming are additional capabilities of the BSCAN standard.
The extension of the BSCAN test to the system backplane adds important testing and ISP/ISC capabilities during the debug phase, production, maintenance and updating, even long after the system installation.
The Boundary Scan Test has been able to verify the LVDS capacitively-coupled circuits. The IEEE 1149.6 recently introduced extension of the IEEE 1149.1 often called AC-EXTEST can uses dot6-compliant devices driving and sensing the differential ac-coupled sending and capturing pulses of data. All the failures of an LVDS capacitively-coupled network (for example, an open net, shorted net to ground/power, missing or short capacitors, etc.) can be detected by the analysis of the data pulses at receiover side.
Further applications are possible in those cases where the UUT includes a local CPU, selected in functional mode, then the system stimulates and/or checks the state of the board through the Fixture card during the functional tests in “full-speed mode”, resident in the firmware of the board itself. This approach provides the Customer with important opportunities for test automation in production. For BSCAN DFT design: go to Services page.
- Click here to open the Boundary Scan (JTAG) Test brochure
- Click here to open the BSCAN test for beginners, how a bscan test can do on a bscan fixtures (Italian language)
How and where You can use JTAG
Advantages in Engineering and in Production
The BSCAN (JTAG) Test have the target of reduce to design to market time and the overall (design and production) costs. The JTAG test can be used both in engineering departements and in production planes.
The JTAG test:
- Make You able to check Your design without manufacturing issue, reducing the first prototypes debug time.
- Make Your production able to build and test any types of board, simple or complex, without an high skill, reducing the learning time and the interation between production and engineering for problem solving.
Click here to see some videos that illustrate how You can use the Jtag Tools in development phase to debug hardware parts of a board, performing manual and automatic connection and stuck tests or functional tests in Python Language.
In the JTAG “world” the are a lot of tools, oriented both the engineers and the producers:
- The BSCAN Engineering tools have low cost and can be used in short time, these have the goal to make simple to drive, to observe, to check connection on the UUT board when You have some doubts due to functional issues. It doesn’t require any special controller, XILINX Platform Cable USB II and ALTERA USB blaster may be used.
- The BSCAN Engineering tools, using diagnostics tool, make simple the fixing of any issues on digital section of an UUT board. Using a structural approch the test is oriented to found manufacturing problems without involving the functionality of the complex componenets, CPU firmware and FPGA user defined function. The conseguence is the reduction of knowlege needed to the BSCAN operators to perform the board test and the issues solving.
The tests can be developed by users or by a design services. Using a design service the HW/SW tools required to just run test are fairly inexpensive.