PCIE to IOBUS SDK

PCIe to General Pourpuse I/O Bus Bridge (PCIe target), Drivers, QSYS and Demo Sources
The GPIO-BUS interface provides a parallel bus with 32 bits data lines, 8 bit address bus lines, controls (RD#, WR#, CS0# , CS1#), auxiliary signals (WAIT#, INT#).

The bus cycle timing can be defined by a control register, setup, hold and pulse width can be changed by user allowing bus cycle time from 48ns to 768ns with 16ns steps. Additional delay can be added by WAIT# signal.

The system includes VHDL source, QSYS design, command line demo source and executable, fpga loadable files (both EP4CGX15BF14C7N and EP4CGX30BF14C6N fpga).

The loading of system on the FPGA needs an USB blaster, some PCIE board (mini PCIE and PCIE on cables) require also a MBBA adapter.

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